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Lattice Semiconductor
CSIX-to-PI40 IP Core User’s Guide
Functional Simulation under ModelSim (PC Platform)
Note: The following procedures are shown using the ORCA ? Series 4 version of the CSIX-to-PI40 core. For other
device versions, refer to the Readme release notes included in that evaluation package.
The RTL simulation environment contains a testbench and a simple application that uses the CSIX-to-PI40 IP core.
The application consists of SERDES loopback function. The application instantiates the IP core, an ORCA
ORSO82G5 module and an ORCA SYSBUS module. The instantiated name of the application is called
“orso82g5_chip”. The testbench includes a CSIX driver, a CSIX monitor, a Motorola Power PC driver, and an
instantiation of the “orso82g5_chip” application. The CSIX driver sends 82 CSIX frames to the user application. The
CSIX monitor inspects CSIX frames transmitted by the application and dumps the results to a ?le called
“cmon_out.dat” in the local simulation directory. The PowerPC driver sends register initialization information and
dumps its results to a ?le called “mpu_out” in the local simulation directory. The following procedure describes the
method for running a simulation of the user application.
A simulation script ?le is provided in the "eval\con?g1\simulation\modelsim\scripts" directory for RTL simulation.
The script ?le vsim_rtl.bat uses precompiled models provided with this package. The CSIX-to-PI40 and testbench
models have been compiled into the work directory in directory “eval\con?g1\simulation\modelsim\rtl”. The ORCA
gate models, ORSO82G5 models, and ORCA SYSBUS models are delivered with the ispLEVER software and the
ORSO82G5 design kit.
Simulation Procedures
1. Launch ModelSim.
2. Using the main GUI, change the directory location.
Select: File_Change Directory_eval\simulation
3. Execute Simulation Macro
Select: Macro _ Execute Macro _ scripts\eval_sim_csix2pi40.do
The pre-compiled model provided in this IP evaluation package does not work with the OEM version of ModelSim
embedded in the ispLEVER software. For more information on how to use ModelSim, please refer to the ModelSim
User’s Manual.
Core Implementation
Lattice’s CSIX-to-PI40 evaluation package includes a simple CSIX user application to demonstrate the process of
synthesizing, mapping, and routing a design using the CSIX-to-PI40 IP core. The application consists of the basic
CSIX-to-PI40 IP core, a verilog module that instantiates the ORSO82G5_IPC2 component, and a verilog module
that instantiates the ORCA4 SYSBUS component, thereby providing a Motorola Power PC interface to the core’s
register interface. This example user application is illustrated in the ?gure below. Once the user is familiar with the
core implementation process, the “real” user application can replace the example application.
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